Verification of System Architectures Using Modal Logics and Formal Model Checking Techniques

An application of formal model checking techniques for developing analysis and assessment mechanisms for system architectures developed in accordance with the DoD Architecture Framework (DoDAF) is presented. The use of temporal logics for capturing a system’s correctness requirements and the use of an architecture design process to refine these specifications are proposed. A computer-aided verification approach is described that employs the executable model, derived from the framework products, and the formal logic statements to establish correctness of the developed system architecture. The approach is presented with the help of an illustrative example.